Semiconductor silicon wafers (hereinafter, referred to as wafers) have typically been used as a substrate with an integrated circuit. In particular, it is desirable for a region where the integrated circuit is formed to have no defects.
Examples of defects contained in the wafers include grown-in defects, which are incorporated during production of a semiconductor single crystal by the CZ method or the like. The defects include a vacancy, in which an atom is missing from a regular crystal lattice site, and interstitial silicon, in which an atom is located between lattice sites.
A region containing many vacancies is called V-region; a region containing many interstitial silicons is called I-region. Between the V-region and the I-region is present N-region, which contains no (or few) vacancies and interstitial silicons. It is assumed that the concentrations of vacancies and interstitial silicons are determined by a relationship between a crystal pulling rate (a growth rate) in the CZ method and a temperature gradient near a solid-liquid interface of a crystal. The N-region can include an area where defects called oxidation induced stacking faults (OSFs) are generated. N-region free from the OSFs is desirably used for producing the integrated circuit devices.
It is important for production of semiconductor single crystals to control the crystal defect regions. Thus, a technique for detecting and evaluating grown-in defects is required.
Many studies have been reported on the technique for detecting and evaluating grown-in defects.
For example, Patent Literatures 1 and 2 disclose methods that include subjecting a wafer segment to heat treatment, measuring an oxide precipitate density in the wafer, and determining a crystal defect region based on the measured value.
Moreover, Patent Literature 3 discloses a method that includes contaminating the surface of a wafer with Fe to visually identify a crystal defect-free region in a silicon single crystal.